藍天,山岳,雲彩

星期日, 5月 06, 2007

define NUM_STATE_BITS 2
`define IDLE 2'b00
`define INIT 2'b01
`define COMPUTE1 2'b10
`define COMPUTE2 2'b11
module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;
initial
clk = 0;always
#50 clk = ~clk;always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;endmodule
module slow_div_system(pb,ready,x,y,r2,sysclk);
input pb,x,y,sysclk;
output ready,r2;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2;
reg [`NUM_STATE_BITS-1:0] present_state;always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x; ready = 1; if (pb) begin @(posedge sysclk) enter_new_state(`INIT); r2 <= @(posedge sysclk) 0; while (r1 >= y)
begin
@(posedge sysclk) enter_new_state(`COMPUTE1);
r1 <= @(posedge sysclk) r1 - y; @(posedge sysclk) enter_new_state(`COMPUTE2); r2 <= @(posedge sysclk) r2 + 1; end end end task enter_new_state; input [`NUM_STATE_BITS-1:0] this_state; begin present_state = this_state; #1 ready=0; end endtaskalways @(posedge sysclk) #20 $display("%d r1=%d r2=%d pb=%b ready=%b", $time, r1,r2, pb, ready); endmodulemodule top; reg pb; reg [11:0] x,y; wire [11:0] quotient; wire ready; integer s; wire sysclk; cl #20000 clock(sysclk); slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);initial begin pb= 0; x = 0; y = 2; #250; @(posedge sysclk); for (x=0; x<=14; x = x+1) begin @(posedge sysclk); pb = 1; @(posedge sysclk); pb = 0; @(posedge sysclk); wait(ready); @(posedge sysclk); if (x/y === quotient) $display("ok"); else $display("error x=%d y=%d x/y=%d quotient=%d",x,y,x/y,quotient); end $stop; end endmodule

心得：由於第一次接觸Verilog語法，對於指令及語法流程皆不是很了解，剛開始我先針對除法機的流程圖及程式的參考範例做深入的認識與研究，並將流程圖與程式改為乘法機模式。從Verilog語法的相關書籍中，我了解程式的架構與指令的介紹，並從程式的註解中去了解其流程，完成了乘法機的行為模式。最後對Verilog語法有初步的認識，但這只是一部分而已，未來將針對混合及結構模式做了解，相信這對我未來會有很好的幫助。

標籤：除法器ASM圖~程式~輸出結果~